There are many examples of floating gate digital memories, whereby the threshold voltage of the floating gate transistors is changed by significant amounts, in the order of a few volts. One logic state is represented by a wide range of thresholds and the other logic state(s) is represented by a different range(s) of thresholds. Information is read from the cell generally by determining whether the transistor conducts or does not conduct when the transistor is biased into a predetermined read condition.
Analog storage, on the other hand, requires that small or continuous changes be made to the threshold of the floating gate transistor, and requires that the reading of the transistor give a determination of an actual voltage from the transistor, or an indication of how conductive the transistor is. Examples of analog storage can be found in U.S. Pat. No. 4,627,027 (Rai), U.S. Pat. No. 4,890,259 (Simko), 4,989,179 (Simko), U.S. Pat. No. 5,220,531 (Blyth), U.S. Pat. No. 5,241,494 (Blyth), U.S. Pat. No. 5,294,819 (Simko), and U.S. Pat. No. 5,973,956 (Blyth).
The present invention provides a means by which an analog storage array configuration and a digital storage array configuration are produced from the same cell technology.
In accordance with the present invention, a semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, and the source lines are diffusion lines.
In one embodiment, the local bitlines are from a first layer metal and the global bitlines are from a second layer metal.
In another embodiment, the cells coupled to a row of local bitlines form a segment block, and the memory further includes a first plurality of interconnect lines in each segment block, each interconnect line electrically connecting together the source lines within each segment block. Each of a second plurality of interconnect lines in each segment block electrically connects the program gate lines within each segment block. The first and second plurality of interconnect lines are from first layer metal.
In another embodiment, the memory further includes a first horizontally extending interconnect line in each segment block, electrically connecting the first plurality of interconnect lines. A second horizontally extending interconnect line in each segment block electrically connects the second plurality of interconnect lines together. The first and second horizontally extending interconnect lines are from first layer metal.
In another embodiment, each segment block has first and second rows of segment select transistors, the first row of segment select transistors providing electrical connection between the global bitlines and one half of the local bitlines in the segment block when selected, and the second row of segment select transistors providing electrical connection between the global bitlines and the remaining half of the local bitlines in the segment block when selected.
In another embodiment, a gate terminal of each of the segment select transistors in the first row of segment select transistors are connected together forming a first continuous segment select line, and a gate terminal of each of the segment select transistors in the second row of segment select transistors are connected together forming a second continuous segment select line. The first and second segment select lines are from third layer polysilicon.
In accordance with another embodiment of the present invention, a semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The drain regions of the cells along each column are connected to a bitline. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, the source lines are diffusion lines, and the bitlines are from a first layer metal.
In another embodiment, the rows of cells are divided in a predesignated number of groups of rows, each group of rows forming a segment block, and the memory further includes a first plurality of vertically extending interconnect lines in each segment block, each of the first plurality of interconnect lines electrically connecting together the source lines within each segment block. The first plurality of interconnect lines are from first layer metal.
In another embodiment, the memory further includes a first horizontally extending interconnect line in each segment block, electrically connecting the first plurality of interconnect lines. Each of a second plurality of horizontally extending interconnect lines in each segment block electrically straps one or more of the program gate lines. The first horizontally extending interconnect line and the second plurality of interconnect lines are from second layer metal.
In another embodiment, every source line is located between two program gate lines, and the drain regions of every two adjacent cells along each column are connected to a bitline via a drain contact such that each row of drain contacts is located between two select gate lines.
In another embodiment, each cell is a split-gate triple-polysilicon cell.
In another embodiment, one or more cells are programmed by biasing the one or more cells so as to induce in each of the one or more cells injection of hot electrons from a source-side of a channel region to the floating gate.
In another embodiment, the rows of cells are divided into a predesignated number of groups of rows, and each group of rows forms a segment block. All cells in a first segment block are simultaneously erased by biasing the cells in the first segment block so as to induce in each cell tunneling of electrons from the floating gate to the source region.
In accordance with yet another embodiment of the present invention, a method of manufacturing a first and second semiconductor memory array configurations wherein each array configuration includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal, includes the acts of: forming a plurality of rows of continuous program gate lines, each row of program gate line forming the program gate terminals of the cells along the row, the program gate lines being from a second layer polysilicon; forming a plurality of rows of continuous select gate lines, each row of select gate line forming the select gate terminals of the cells along the row, the select gate lines being from a third layer polysilicon; forming a plurality of rows of continuous source lines, each source line forming the source regions of the cells along the row, the source lines being from diffusion; wherein the first array configuration is obtained by: forming a plurality of local bitlines, the cells along each column being divided into a predesignated number of groups, the drain regions of the cells in each group being connected to one of the local bitlines extending across the cells in the group of cells; and forming a plurality of global bitlines along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the two columns of cells, wherein the local bitlines are from a first layer metal and the global bitlines are from a second layer metal.
In another embodiment, the second array configuration is obtained by forming a plurality of bitlines, the drain regions of the cells along each column being connected to one of the plurality of bitline, the bitlines being from a first layer, metal.
In another embodiment, the first array configuration the cells coupled to a row of local bitlines form a segment block, and the method further includes: forming a first plurality of interconnect lines in each segment block, each of the first plurality of interconnect lines electrically connecting together the source lines within each segment block; and forming a second plurality of interconnect lines in each segment block, each of the second plurality of interconnect lines electrically connecting the program gate lines within each segment block, wherein the first and second plurality of interconnect lines are from first layer metal.
In another embodiment, the method further includes: forming a first horizontally extending interconnect line in each segment block, the first interconnect line electrically connecting the first plurality of interconnect lines; and forming a second horizontally extending interconnect line in each segment block, the second interconnect line electrically connecting the second plurality of interconnect lines together, wherein the first and second horizontally extending interconnect lines are from first layer metal.
In another embodiment, the method further includes forming first and second rows of segment select transistors in each segment block, the first row of segment select transistors providing electrical connection between the global bitlines and one half of the local bitlines in the segment block when selected, and the second row of segment select transistors providing electrical connection between the global bitlines and the remaining half of the local bitlines in the segment block when selected.